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ST24/25C02, ST24C02R ST24/25W02
SERIAL 2K (256 x 8) EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: - 3V to 5.5V for ST24x02 versions - 2.5V to 5.5V for ST25x02 versions - 1.8V to 5.5V for ST24C02R version only HARDWARE WRITE CONTROL VERSIONS: ST24W02 and ST25W02 TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4 BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH-UP PERFORMANCES ST24C/W02 are replaced by the M24C02 ST25C/W02 are replaced by the M24C02-W ST24C02R is replaced by the M24C02-R DESCRIPTION This specification covers a range of 2K bits I2C bus EEPROM products, t he ST24/25C02, the ST24C02R and ST24/25W02. In the text, products are referred to as ST24/25x02, where "x" is: "C" for Standard version and "W" for hardware Write Control version. Table 1. Signal Names
E0-E2 SDA SCL MODE WC VCC VSS November 1997
This is information on a product still in production but not recommended for new design
8 1
PSDIP8 (B) 0.25mm Frame
8 1
SO8 (M) 150mil Width
Figure 1. Logic Diagram
VCC
3 E0-E2 SCL MODE/WC* ST24x02 ST25x02 ST24C02R SDA
Chip Enable Inputs Serial Data Address Input/Output Serial Clock Multibyte/Page Write Mode (C version) Write Control (W version) Supply Voltage Ground
Note: WC signal is only available for ST24/25W02 products.
VSS
AI00788D
1/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x02 ST25x02 ST24C02R E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI00789D
ST24x02 ST25x02 ST24C02R
VCC MODE/WC SCL SDA
E0 E1 E2 VSS
1 2 3 4
8 7 6 5
AI00790E
VCC MODE/WC SCL SDA
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)
(3) (2)
Value -40 to 125 -65 to 150
Unit C C C V V V V
(SO8 package) (PSDIP8 package)
40 sec 10 sec
215 260 -0.6 to 6.5 -0.3 to 6.5 4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 ). 3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont'd) The ST24/25x02 are 2K bit electrically erasable programmable memories (EEPROM), organized as 256 x 8 bits. They are manufactured in SGSTHOMSON's Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The memories operate with a power supply value as low as 1.8V for the ST24C02R only. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. The memories are compatible with the I 2C standard, two wire serial interface which uses a bi-direc2/16
tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This is used together with 3 chip enable inputs (E2, E1, E0) so that up to 8 x 2K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.
ST24/25C02, ST24C02R, ST24/25W02
Table 3. Device Select Code
Device Code Bit Device Select
Note: The MSB b7 is sent first.
Chip Enable b4 0 b3 E2 b2 E1 b1 E0
RW b0 RW
b7 1
b6 0
b5 1
Table 4. Operating Modes (1)
Mode Current Address Read Random Address Read Sequential Read Byte Write Multibyte Write Page Write
(2)
RW bit '1' '0' '1' '1' '0' '0' '0'
MODE X X X X VIH VIL
Bytes 1 1 1 to 256 1 4 8
Initial Sequence START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' Similar to Current or Random Mode START, Device Select, RW = '0' START, Device Select, RW = '0' START, Device Select, RW = '0'
Notes: 1. X = VIH or VIL 2. Multibyte Write not available in ST24/25W02 versions.
When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Chip Enable (E2 - E0). These chip enable inputs are used to set the 3 least significant bits (b3, b2, b1) of the 7 bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code. Mode (MODE). The MODE input is available on pin 7 (see also WC feature) and may be driven dynamically. It must be at VIL or VIH for the Byte Write mode, VIH for Multibyte Write mode or VIL for Page Write mode. When unconnected, the MODE input is internally read as a VIH (Multibyte Write mode). Write Control (WC). An hardware Write Control feature (WC) is offered only for ST24W02 and ST25W02 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC = VIL) the internal write protection. When unconnected, the WC input is internally read as VIL and the memory area is not write protected.
3/16
ST24/25C02, ST24C02R, ST24/25W02
SIGNAL DESCRIPTIONS (cont'd) The devices with this Write Control feature no longer support the Multibyte Write mode of operation, however all other write modes are fully supported. Refer to the AN404 Application Note for more detailed information about Write Control feature. DEVICE OPERATION I2C Bus Background The ST24/25x02 support the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24/25x02 are always slave devices in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x02 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x02 and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the ST24/25x02 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave ST24/25x02, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20 VCC 16 RL RL
RL max (k)
12 MASTER 8
SDA SCL CBUS
CBUS 4 VCC = 5V 0 100 200 CBUS (pF) 300 400
AI01100
4/16
ST24/25C02, ST24C02R, ST24/25W02
Table 5. Input Parameters (1) (TA = 25 C, f = 100 kHz )
Symbol CIN CIN ZWCL ZWCH tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance (ST24/25W02) WC Input Impedance (ST24/25W02) Low-pass filter input time constant (SDA and SCL) VIN 0.3 VCC VIN 0.7 VCC 5 500 100 Test Condition Min Max 8 6 20 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested.
Table 6. DC Characteristics (TA = 0 to 70C, -20 to 85C or -40 to 85C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current (ST24 series) Supply Current (ST25 series) Supply Current (Standby) (ST24 series) Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 100kHz (Rise/Fall time < 10ns) VCC = 2.5V, fC = 100kHz VIN = VSS or VCC, VCC = 5V VIN = VSS or VCC, VCC = 5V, fC = 100kHz VIN = VSS or VCC, VCC = 2.5V VIN = VSS or VCC, VCC = 2.5V, fC = 100kHz VIN = VSS or VCC, VCC = 3.6V VIN = VSS or VCC, VCC = 3.6V, fC = 100kHz VIN = VSS or VCC, VCC = 1.8V VIN = VSS or VCC, VCC = 1.8V, fC = 100kHz -0.3 0.7 VCC -0.3 VCC - 0.5 IOL = 3mA, VCC = 5V IOL = 2.1mA, VCC = 2.5V IOL = 1mA, VCC = 1.8V Min Max 2 2 2 1 100 300 5 50 20 60 10 20 0.3 VCC VCC + 1 0.5 VCC + 1 0.4 0.4 0.3 Unit A A mA mA A A A A A A A A V V V V V V V
ICC
ICC1
ICC2
Supply Current (Standby) (ST25 series)
ICC3
Supply Current (Standby) (ST24C02R)
ICC4
Supply Current (Standby) (ST24C02R)
VIL VIH VIL VIH
Input Low Voltage (SCL, SDA) Input High Voltage (SCL, SDA) Input Low Voltage (E0-E2, MODE, WC) Input High Voltage (E0-E2, MODE, WC) Output Low Voltage (ST24 series)
VOL
Output Low Voltage (ST25 series) Output Low Voltage (ST24C02R)
5/16
ST24/25C02, ST24C02R, ST24/25W02
Table 7. AC Characteristics (TA = 0 to 70C, -20 to 85C or -40 to 85C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL1 tCHDX
(1)
Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time
Parameter
Min
Max 1 300 1 300
Unit s ns s ns s s s s s ns s s
Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time
4.7 4 4 0 4.7 250 4.7 4.7 0.3 300 100 10 3.5
tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV
(2)
s ns kHz ms
tCLQX fC tW
(3)
Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. 3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages 50ns 0.2VCC to 0.8VCC
DEVICE OPERATION (cont'd) The 4 most significant bits of the device select code are the device type identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 3 bits identify the specific memory on the bus. They are matched to the chip enable signals E2, E1, E0. Thus up to 8 x 2K memories can be connected on the same bus giving a memory capacity total of 16K bits. After a START condition any memory on the bus will identify the device code and compare the following 3 bits to its chip enable inputs E2, E1, E0. The 8th bit sent is the read or write bit (RW), this bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time.
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.7VCC 0.3VCC
AI00825
0.2VCC
6/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 5. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE
tCLCH
tDXCX
tCHDH
tDHDL STOP & BUS FREE
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
tDHDL SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795
7/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 6. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
Write Operations The Multibyte Write mode (only available on the ST24/25C02 and ST24C02R versions) is selected when the MODE pin is at VIH and the Page Write mode when MODE pin is at VIL. The MODE pin may be driven dynamically with CMOS input levels. Following a START condition the master sends a device select code with the RW bit reset to '0'. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides access to 256 bytes of the memory. After receipt of the byte address the device again responds with an acknowledge.
8/16
For the ST24/25W02 versions, any write command with WC = 1 will not modify the memory content. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independant of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either VIH or VIL, to minimize the stand-by current.
ST24/25C02, ST24C02R, ST24/25W02
Multibyte Write. For the Multibyte Write mode, the MODE pin must be at VIH. The Multibyte Write mode can be started from any address in the memory. The master sends from one up to 4 bytes of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The duration of the write cycle is tW = 10ms maximum except when bytes are accessed on 2 rows (that is have different values for the 6 most significant address bits A7A2), the programming time is then doubled to a maximum of 20ms. Writing more than 4 bytes in the Multibyte Write mode may modify data bytes in an adjacent row (one row is 8 bytes long). However, the Multibyte Write can properly write up to 8 consecutive bytes only if the first address of these 8 bytes is the first address of the row, the 7 following bytes being written in the 7 following bytes of this same row. Page Write. For the Page Write mode, the MODE pin must be at VIL. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the 5 most significant memory address bits (A7-A3) are the same. The master sends from one up to 8 bytes of data, which are each acknowledged by the memory. After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request.
Figure 7. Write Cycle Polling using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by ST24xxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01099B
9/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 8. Write Modes Sequence (ST24/25C02 and ST24C02R)
ACK BYTE WRITE DEV SEL
ACK DATA IN
ACK
BYTE ADDR R/W ACK ACK
START
ACK DATA IN 1 DATA IN 2
MULTIBYTE AND PAGE WRITE
DEV SEL
BYTE ADDR R/W
START
ACK DATA IN N
ACK
STOP
STOP
AI00793
Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master. The sequence is as follows: - Initial condition: a Write is in progress (see Figure 7). - Step 1: the master issues a START condition followed by a device select byte (1st byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1).
Read Operations Read operations are independent of the state of the MODE pin. On delivery, the memory content is set at all "1's" (or FFh). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a memory address with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Random Address Read. A dummy write is performed to load the address into the address counter, see Figure 10. This is followed by another START condition from the master and the byte address is repeated with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed. The master have to NOT acknowledge the byte output, but terminates the transfer with a STOP condition.
10/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W02)
WC ACK BYTE WRITE DEV SEL ACK DATA IN ACK
BYTE ADDR R/W
WC ACK PAGE WRITE DEV SEL ACK DATA IN 1 ACK DATA IN 2
START
BYTE ADDR R/W
WC (cont'd) ACK PAGE WRITE (cont'd) DATA IN N ACK
START
STOP
STOP
AI01101B
Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automat-
ically incremented after each byte output. After a count of the last memory address, the address counter will 'roll- over' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24/25x02 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25x02 terminate the data transfer and switches to a standby state.
11/16
ST24/25C02, ST24C02R, ST24/25W02
Figure 10. Read Modes Sequence
ACK CURRENT ADDRESS READ DEV SEL
NO ACK DATA OUT
START
R/W
ACK RANDOM ADDRESS READ DEV SEL *
ACK DEV SEL *
STOP
ACK
NO ACK DATA OUT
BYTE ADDR
START
R/W
START
R/W
ACK SEQUENTIAL CURRENT READ DEV SEL
ACK
ACK
NO ACK
DATA OUT 1 R/W
DATA OUT N
START
ACK SEQUENTIAL RANDOM READ DEV SEL *
ACK DEV SEL *
ACK
ACK
BYTE ADDR
DATA OUT 1
START
R/W
START
R/W
ACK
NO ACK
DATA OUT N
STOP
AI00794C
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
12/16
STOP
STOP
ST24/25C02, ST24C02R, ST24/25W02
ORDERING INFORMATION SCHEME
Example:
ST24C02
M
1
TR
Operating Voltage ST24C02 ST24W02 ST25C02 ST25W02 ST24C02R 3V to 5.5V 3V to 5.5V 2.5V to 5.5V 2.5V to 5.5V 1.8V to 5.5V Standard
Range Hardware Write Control Standard Hardware Write Control Standard
Package B M PSDIP8 0.25mm Frame SO8 150mil Width
Temperature Range 1 5* 6 3* 0 to 70 C -20 to 85 C -40 to 85 C -40 to 125 C TR
Option Tape & Reel Packing
Notes:
3 * Temperature range on special request only. 5 * Temperature range for ST24C02R only.
Parts are shipped with the memory content set at all "1's" (FFh). For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
13/16
ST24/25C02, ST24C02R, ST24/25W02
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N
PSDIP8
mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 7.62 - 6.00 2.54 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.00 8 3.80 0.100 0.300 Typ
inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.118 8 0.150
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale
14/16
ST24/25C02, ST24C02R, ST24/25W02
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb Typ A A1 B C D E e H h L N CP
SO8
mm Min 1.35 0.10 0.33 0.19 4.80 3.80 1.27 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ
inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale
15/16
ST24/25C02, ST24C02R, ST24/25W02
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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